The popularity of battery-operated equipment, and the demand for smaller integrated circuit devices having lower power consumption (with consequent longer periods between battery replacement or recharging), has given rise to a need for reducing power consumption in the devices used in such equipment. One technique that has been developed involves supplying full power to a device during periods of so-called “normal” operation, and placing the device in a low power consumption mode (sometimes referred to as “inactive,” “power down,” or “sleep” mode) during intervening non-operating periods.
U.S. Pat. No. 5,619,204 describes an analog-to-digital converter (ADC) with optional low power mode that is controlled by monitoring the state of a “conversion start” (CONVST) signal with respect to the conversion completion point. U.S. Pat. No. 5,714,955 ('955 Patent) describes dual function control circuitry for effecting the switchover between operating modes of a serial ADC. The control signals used to trigger this switchover between operating modes are signals associated with the conversion process and not with the serial data transfer.
FIG. 1 is a block diagram of an ADC of the prior art (generally depicted by the numeral 100) that is configured to accommodate operating mode programming, in this case for power-down mode control. A CLK (clock) signal 101 is used to synchronise the conversion operation, and a CONV (conversion) signal 102 is used to initiate the conversion operation. The CLK 101 and CONV 102 signals are provided as inputs to internal control logic 103 that controls operation of the SAR (successive approximation register) and parallel to serial converter logic 104. The serial output data 108 of the device 100 is derived by shifting out the SAR contents serially after the conversion is complete.
The CLK 101 and CONV 102 signals also serve to produce power-down and power-up commands. They thus serve as dual-function pins. However, these signals do not produce these power-up and power-down commands when operating in the usual manner across the serial interface. The manner in which these signals must be asserted with respect to each other is not easily configured over a standard serial interface, and cannot provide power-down and power-up commands when standard serial communication is taking place. Instead, the signals are asserted as shown in the timing diagram of FIG. 2.
When CLK 201 is low, two CONV 202 pulses command the ADC to enter a first power-down mode, in this case a reduced power consumption mode denominated the NAP mode 203. When CLK 201 remains low, two additional CONV 202 pulses are required to place the part in a second power-down mode, in this case the SLEEP mode 204, consuming even less power than the NAP mode 203. The timing of CONV and CLK are not easily generated over a standard serial interface with a microcontroller, and are not available from a DSP in the manner required.
The closest known practice exists in a family of serial ADCs manufactured by Analog Devices, Inc. Shutdown is controlled via the state of “chip select” (CS) when the device is in read-only mode. When CS is low, the device is fully powered up, and when CS is high the device is fully powered down. This means that shutdown is enforced after each conversion, and so the required power-up time must be allowed before each conversion, slowing down the overall throughput of the device. Conventional ADC circuits typically use a dedicated input in order to implement a power-down function, and this utilization of single-purpose inputs extends to mode-control programming generally. This requirement for a dedicated input increases the number of lines in the chip package.
A need thus arises for a mode control implementation that does not require a dedicated input or complex, multi-line protocol, and thus does not interfere with device throughput.